2023

mux_2_ex_1.sv

+`timescale 1ns/1ns
+// specify what "#1" means!
+
+module mux_2_ex_1(
+    input [1:0] a,
+    input [1:0] b,
+    input sel,
+    output [1:0] o
+);
+
+// if sel = 1, choose a, otherwise b
+assign o = sel ? a : b;
+
+endmodule
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mux_2_ex_2.sv

+`timescale 1ns/1ns
+// specify what "#1" means!
+
+module mux_2_ex_2(
+    input [1:0] a,
+    input [1:0] b,
+    input sel,
+    output reg [1:0] o
+);
+
+// if sel = 1, choose a, otherwise b
+always @(a or b or sel) begin
+    case (sel)
+        1'b1: begin
+            o = a;
+        end
+        1'b0: begin
+            o = b;
+        end
+        // default: begin // See the difference with and without "default"
+        //     o = b;
+        // end
+    endcase
+end
+
+endmodule
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mux_2_ex_3.sv

+`timescale 1ns/1ns
+// specify what "#1" means!
+
+module mux_2_ex_3(
+    input [1:0] a,
+    input [1:0] b,
+    input sel,
+    output reg [1:0] o
+);
+
+// if sel = 1, choose a, otherwise b
+// "always_comb" is the preferred way!
+// avoid old fashioned "always"
+always_comb begin: mux
+    if (sel == 1'b1) begin
+        o = a;
+    end
+    else begin
+        o = b;
+    end    
+end
+
+endmodule
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mux_2_tb.sv

+`timescale 1ns/1ns
+// specify what "#1" means!
+
+module mux_2_tb;
+    reg [1:0] a;    // input a
+    reg [1:0] b;    // input b
+    reg sel;        // selector sel
+    wire [1:0] o1;  // output o of design 1
+    wire [1:0] o2;  // output o of design 2
+    wire [1:0] o3;  // output o of design 3
+    integer i;      // counter
+
+    // Connect testbench to a design
+    mux_2_ex_1 mux_2_1 (
+        .a (a),
+        .b (b),
+        .sel (sel),
+        .o (o1)
+    );
+    // Connect testbench to a design
+    mux_2_ex_2 mux_2_2 (
+        .a (a),
+        .b (b),
+        .sel (sel),
+        .o (o2)
+    );
+    // Connect testbench to a design
+    mux_2_ex_3 mux_2_3 (
+        .a (a),
+        .b (b),
+        .sel (sel),
+        .o (o3)
+    );
+
+    // Stimulus block
+    initial begin
+        $display("@Time :: a \tb \tsel\to1\to2\to3");
+	    $monitor("@%4t :: 0x%h\t0x%h\t0b%h\t0x%h\t0x%h\t0x%h", $time, a, b, sel, o1, o2, o3);
+        // sel <= $random;
+        // a <= $random;
+        // b <= $random;
+
+        // Main simulation loop
+        for (i = 1; i < 16; i = i + 1) begin
+            a <= $random;
+            b <= $random;
+            #5 sel <= $random;
+        end
+
+        // After simulations, wait for 5ns and stop simulation
+        // #5 $finish;
+        #5 $stop;
+    end
+  
+endmodule
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