STATE_C is 4-bit

calc_logic.sv

@@ -8,7 +8,7 @@ input [7:0] A, B;
 input [4:0] OP;
 output valid;
 output [7:0] C;
-output [4:0] STATE_C;
+output [3:0] STATE_C;
 reg [7:0] CC;
 // reg [4:0] y, Y;
 reg val;