2023 simple

ones.sv

+module detect_ones_moore(
+    input x,
+    input clk,
+    input rst,
+    output y
+);
+
+reg [1:0] state;
+parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        state <= S0;
+    end
+    else begin
+        case (state)
+            S0: if (x) state <= S1;
+                else state <= S0;
+            S1: if (x) state <= S2;
+                else state <= S0;
+            S2: if (x) state <= S3;
+                else state <= S0;
+            S3: if (x) state <= S3;
+                else state <= S0;
+        endcase
+    end
+end
+
+assign y = (state == S3);
+    
+endmodule

ones_jp.sv

+module ones_jp;
+
+reg x;
+reg clk;
+// reg rst;
+reg rst_n;
+// wire y;
+wire y_t;
+integer i;
+
+localparam period = 20;
+
+detect_ones_moore_t ones_uut_t(
+    .x(x),
+    .clk(clk),
+    .rst_n(rst_n),
+    .y(y_t)
+);
+
+endmodule

ones_t.sv

+module detect_ones_moore_t(
+    input x,
+    input clk,
+    input rst_n,
+    output y
+);
+
+typedef enum logic[1:0] { S0, S1, S2, S3 } state_t;
+state_t state;
+
+always_ff @(posedge clk) begin
+    if (!rst_n) begin
+        state <= S0;
+    end
+    else begin
+        case (state)
+            S0: if (x) state <= S1;
+                else state <= S0;
+            S1: if (x) state <= S2;
+                else state <= S0;
+            S2: if (x) state <= S3;
+                else state <= S0;
+            S3: if (x) state <= S3;
+                else state <= S0;
+        endcase
+    end
+end
+
+assign y = (state == S3);
+    
+endmodule

ones_tb.sv

+module ones_tb;
+
+reg x;
+reg clk;
+reg rst;
+reg rst_n;
+wire y;
+wire y_t;
+integer i;
+
+localparam period = 20;
+
+detect_ones_moore ones_uut(
+    .x(x),
+    .clk(clk),
+    .rst(rst),
+    .y(y)
+);
+
+detect_ones_moore_t ones_uut_t(
+    .x(x),
+    .clk(clk),
+    .rst_n(rst_n),
+    .y(y_t)
+);
+
+// Drive the clk signal
+always begin
+    clk = 1'b1;
+    #10;
+    clk = 1'b0;
+    #10;
+end
+
+always @(posedge clk) begin
+    $monitor("@%4t\t::\t0b%h\t0b%h\t0b%h", $time, rst, x, y);
+
+    #period;
+    rst <= 1'b1;
+    rst_n <= 1'b0;
+    #period;
+    rst <= 1'b0;
+    rst_n <= 1'b1;
+
+    for (i = 0; i < 10; i = i + 1) begin
+        x <= $random;
+        #period;    
+    end
+
+
+    for (i = 0; i < 3; i = i + 1) begin
+        x <= 1'b1;
+        #period;    
+    end
+
+    for (i = 0; i < 3; i = i + 1) begin
+        x <= 1'b0;
+        #period;    
+    end
+
+    $stop;
+end
+    
+endmodule